Communications interfaces for integrated circuit devices are increasingly used to perform test and debug for systems. Often there is a need to control and observe the internal state of integrated circuit devices. This observation feature is needed for debugging software and firmware used to implement a system. However, in a typical case these interfaces are not used in the finished product. The resources required for the debug interface take away from resources that could be otherwise used for additional product features. As a result it is extremely undesirable to dedicate substantial board space and area, wires and interface pins, to the communications interface used for debugging the system. While the communications interface is necessary to validate the system, the impact on system resources must be minimized.
Many test and debug communications interfaces have been designed and currently are in use. The JTAG interface promulgated by the Joint Test Action Group, covered by the IEEE 1149.1 specification entitled “Standard Test Port and Boundary Scan Architecture”, the Inter-Integrated Circuit (I2C) bus interface, the SMBus interface, the SPI bus interface, are all examples of various prior known solutions. Each of these communications protocols requires multiple wires and some use a dedicated clock or strobe line. These multiple wire interfaces also require multiple routing channels that require valuable system board space and routing space within the integrated circuits or circuit boards. Further, when multiple wire interfaces are used, there is an increased likelihood of errors or failures due to shorting and crosstalk problems at both the board and device level. Some known prior approach interfaces further require synchronous communications with critical timing, and some may require precise on-board timing circuits, some solutions may require additional precision timing sources such as crystal oscillators. If the interface circuitry inside the integrated circuit is complex, valuable integrated circuit die area is required for the communications interface, integrated circuit die area that is at a premium and which could otherwise be used for providing additional features to the integrated circuit and the corresponding system.
A prior single wire communications interface is described by U.S. patent application Ser. No. 13/049,694, entitled “Serial Interface”, published Sep. 20, 2012, which is co-owned with the present application, and which is hereby incorporated in its entirety herein by reference.
Improvements in the communications interface between devices are therefore needed to address the deficiencies and the disadvantages of the known prior approaches. Solutions are needed that have minimum wiring, pin and device area requirements, that are robust, that provide reliable data communications with sufficient speed, that are low in cost, and that are easy to implement and use.